A play with MyHDL

Long time since a update. Sorry everyone for the late updates.

This week is full of surprises for me. I started using MyHDL and I came to know how things work exactly. I will explain my experience with different attributes and modules one by one. I will be using verilog much in my blog because I feel comfortable using verilog.

1.

The MyHDL signal is similiar to VHDL signal. I felt an analogy of the MyHDL signal’s next attribute with the non blocking Verilog assignments.

 

always@(clk)

       a <= b   // non blocking assignment

       c <= d   // non blocking assignment

Now coming to MyHDL analogy with VHDL Signal

@always_seq(clk.posedge, reset = reset)

def logic():

    a.next = b // non blocking assignment

    c.next = d // non blocking assignment

Where a,b,c,d are Signals in MyHDL.

2.

I was practising with MyHDL and I had to assign some statement like :

assign a = b

assign c = d

I did a straight forward assignment and it do not work. I contacted Chris Felton with my problem and he provided a nice way to do such assignments.

@always_comb

def assign():

    a.next = b

    c.next = d

return assign 

3.

Following the journey, I tried to check whether MyHDL accepts a 2-D array as input in the module. Unfortunately I was unable to convert my code because Verilog do not accept 2-D array inputs, it was a mistake from me to expect such feature. This can be a new feature in MyHDL soon.

Then I tried to give a List of Signals as input and it eventually failed during conversion. We all know verilog do not accept list of signals as input. unless input is declared as wire

i.e input wire [4:0] inputlist [0:63]

// do not confuse it with 2-D array its a list with 5 bit data in each block

To solve this issue My Mentor Josyb said to use a wrapper which will take N Signals as input wrap them into an array ( not an input array ). Processing them and then unwrapping them.

I also tried a different method shown as follows :

def test():
    iPixelBlock = [Signal(intbv(0, -1 << 11, -(-1 << 11) + 1)) for _ in range(64)]  
    clk = Signal(INACTIVE_HIGH)
    enable_in, enable_out = [Signal(INACTIVE_LOW) for _ in range(2)]
    reset = ResetSignal(1, active=ACTIVE_LOW, async=True)
    inst = huffman(huffman, enable_out, iPixelBlock, enable_in, clk, reset)
    return inst

toVerilog(test)

It works well and everyone knows why it works. List of signals is not an input to the block we are converting.

4.

We have two reference designs on which we have to work.

The VHDL version by Michal Krepa and The verilog version by david klun.

Josyb, Mkatsimpris and I decided to focus more on the VHDL version because the cores in the VHDL version are more modular and scalable. Also, they are very comfortable for independant testing.

The next post will contain my Github link and some modules which I designed for practise.

Thanks for going through the post.

Have a nice day 🙂 .